The present invention relates in general to data processing systems, and in particular, to apparatus and methods for performing floating-point compare operations in data processing systems.
Floating-point compare operations in data processing systems require that the system have the capability to compare two floating-point numbers in which the sign of the operands may either be the same, or may be different. Comparison of two floating-point operands with different signs can easily be done by observing the signs of the operands. However, comparison of two floating-point operands with the same sign is performed by subtracting the absolute value, or modulus, of a first operand from the absolute value of the second operand and then ascertaining the sign of the result to determine the outcome of the comparison.
This subtraction of the magnitudes of the operands is implemented using an adder with an appropriate carry-in. The required carry-in is a function both of the instruction, that is the particular type of comparison being executed, and the operands.
Modern high performance data processing systems employ data-forwarding design techniques in which operands arrive late in an instruction cycle. For example, an instruction that is ready to be issued to an execution unit may depend on a currently executing instruction for one or more of its operands. By snooping the output bus of the execution unit, the instruction waiting to be issued may issue, and then retrieve its operands from the output bus of the execution unit before the operands have been committed to their architected registers. However, in such data-forwarding designs, this creates a critical timing path for the compare operations, because of the added logic levels necessary to generate the carry-in from the operands. Thus, there is a need in the art for mechanisms to provide the required carry-in necessary to perform the floating-point compares, without adding logic levels to the timing path.
The aforementioned needs are addressed by the present invention. Accordingly there is provided, in a first form, a floating-point compare apparatus. In a first embodiment, the apparatus includes adder circuitry operable for receiving first and second source operands, the adder circuitry operable for outputting a difference of a modulus of the first operand and the second operand in response to instruction information and a carry-in bit, wherein the carry-in bit is a sign bit of the second operand. In a second embodiment, the apparatus contains adder circuitry operable for outputting a difference of a modulus of a first input operand and a second input operand in response to an executing instruction and a carry-in bit, wherein the carry-in bit is a sign bit of the second input operand. Also, included is a switch logic operable for outputting the first and second input operands in response to first and second source operands and a first instruction information signal. The switch logic is operable for switching between first and second states for outputting the signals in response to the instruction information signal.
There is also provided, in a second form, a method of method of performing floating-point compares. In a first embodiment, the method includes the step of generating a difference of moduli of first and second source operands in response to a carry-in bit and an instruction information signal, wherein the carry-in bit comprises a sign bit of the second instruction operand. In a second embodiment, the method generates a difference of moduli of first and second input operands in response to a carry-in bit and an executing instruction, wherein the carry-in bit comprises a sign bit of the second input operand. The method also contains the step of switching first and second source operands to output the first and second input operands in response to first and second source operands, wherein the switching step is in response to a first instruction information signal.
Additionally, there is provided, in a third form, a data processing system. In a first embodiment, the data processing system has a central processing unit (CPU) and a memory operable for communicating instructions and operand data to the CPU. The CPU includes instruction decode logic operable for receiving the instructions, and generating an instruction information signal in response thereto, and adder circuitry operable for receiving first and second source operands corresponding to a received instruction, the adder circuitry operable for outputting a difference of a modulus of the first operand and the second operand in response to the instruction information, and a carry-in bit, wherein the carry-in bit is a sign bit of the second operand. In a second embodiment, the data processing system contains a central processing unit (CPU) and a memory operable for communicating instructions and operand data to the CPU, in which the CPU has instruction decode logic operable for receiving the instructions, and generating an instruction information signal in response thereto, switch logic operable for receiving first and second source operands; and adder circuitry operable for receiving first and second input operands from the switch logic. The adder circuitry is operable for outputting a difference of a modulus of the first operand and the second operand in response to an executing instruction and a carry-in bit, wherein the carry-in bit is a sign bit of the second input operand, and wherein the switch logic switches between a first state for outputting the first and second input signals and a second state for outputting the first and second input signals in response to the first instruction information signal.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.